Seal ring structure for radio frequency integrated circuits

ABSTRACT

Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention generally relates to an encapsulation process usedin semiconductor manufacturing and, more particularly, to a method ofencapsulation that improves isolation of radio frequency (RF) signals inthe fabrication of integrated circuits.

[0003] (2) Description of Prior Art

[0004] As integrated circuit (IC) speeds increase, seal rings have beenincorporated into the device encapsulation in order to reduce radiofrequency (RF) interference and signal cross coupling. The seal ring isgrounded or connected to a signal ground such as a DC supply line toeliminate the effect of interference. The seal ring may be part of thedevice packaging scheme; in this case a conductive lid is typicallyconnected to the seal ring. Specific to this invention, the seal ringmay be incorporated into the IC substrate fabrication and may include aconductive covering over the substrate.

[0005]FIG. 1 shows in exploded view a method where the seal ring isincorporated into the device package. A substrate 10 made of ceramicmaterial, for example, has an integrated circuit die 12 attached by aconductive epoxy or eutectic bond. The die 12 is electrically connectedto the substrate 10 using bond wires (not shown). A conductive seal ring14 is attached and grounded by internal connections (not shown). Thepackage is scaled using a lid 16 to prevent penetration by contaminantsand moisture.

[0006]FIG. 2 shows a top view of an IC die 20 where a seal ring 22 isincorporated. A plurality of bonding pads 24 arc shown which may beeither signal inputs or outputs, or DC supply and ground. A portion ofthe circuit containing RF circuits 26 is shown. One problem with thismethod is that signals from the bonding pads 24 may be capacitivelycoupled to the seal ring 22. This may result in unwanted signalinterference appearing at one of the signal input or output bonding pads24. In addition, interference may be coupled to the RF circuit 26resulting in signal distortion.

[0007] Other approaches employing seal rings exist. U.S. Pat. No.5,717,245 to Pedder teaches a system using a dielectric multi-layersubstrate where RF interference is reduced by grounding certain areasand encapsulating the substrate within a conductive seal ring. U.S. Pat.No. 6,028,497 to Allen et al. teaches a system where RF signals arepassed through a network of holes in the base plate of the module. Theholes each consist of a conductive pin surrounded by, but electricallyisolated from, a conductive cylindrical shroud, thereby forming acoaxial connection. A compartmentalized seal ring attached to the top ofthe module segregates different circuit areas of the module. U.S. Pat.Nos. 5,864,092 and 6,105,226 to Gore et al. teach methods employing aleadless chip carrier package where a grounded conductor protrudesbetween input and output signal pads thereby preventing interference.U.S. Pat. No. 5,998,245 to Yu teaches a method where ESD protection isincorporated into a seal ring structure on an IC die. U.S. Pat. No.6,028,347 to Sauber et al. teaches a method where a portion of the sealring is formed in trenches in the semiconductor surface. Anencapsulating plastic covering over the surface fills the trenchesthereby preventing movement of the cover and reducing stresses due tothermal expansion.

SUMMARY OF THE INVENTION

[0008] A principal object of the present invention is to provide amethod that reduces cross coupling between circuits and pads in anintegrated circuit.

[0009] Another object of the present invention is to provide a methodthat prevents cross coupling between circuits caused by the seal ring inan integrated circuit.

[0010] These objects are achieved by using a method where a seal ring isformed by stacking interconnected metal layers along the perimeter ofthe integrated circuit (IC). Discontinuities are formed in the seal ringencapsulating different sections of the IC. There are no overlapsbetween discontinuities in the seal ring thus isolating signals utilizedon different sub-circuits within the IC. To further reduce unwantedsignal coupling, the distances between the seal ring and both signalpads and circuits are enlarged. Electrical connection is made betweenthe deep N-well and the seal ring to encapsulate the substrate andminimized signal coupling to the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings forming a material part of thisdescription, there is shown:

[0012]FIG. 1 schematically illustrating an exploded view cross-sectionalrepresentation of a prior art example employing seal rings;

[0013]FIG. 2 schematically illustrating a top view cross-sectionalrepresentation of a prior art example employing seal rings;

[0014]FIG. 3 schematically illustrating in cross-sectionalrepresentation a preferred embodiment of the present invention;

[0015]FIG. 4 schematically illustrating a top view of a preferredembodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention uses a method where a seal ring is formedby stacking interconnected conducting layers along the perimeter of theintegrated circuit (IC). The embodiment provided herein describes amethod of creating the seal ring and connecting the seal ring to thedeep N-well.

[0017] Refer to FIG. 3, depicting in cross-section a portion of anintegrated circuit die where the seal ring is formed. A substrate 30 isprovided. The substrate layer 30 may contain underlying layers, devices,junctions, and other features (not shown) formed during prior processsteps. The cut line 31 represents the outer edge of the IC die ofinterest. During subsequent processing, the die would be separated froman adjacent IC die (not shown) on the substrate 30 along that cut line31. A deep N-well region 32 is formed as is conventional in the art. Ap+ source/drain (S/D) region 34 formed by conventional techniques isisolated from the remainder of the underlying circuitry (not shown) byshallow trench isolation 36. A silicide 38 is formed over the S/D region34 providing a low resistance connection to the S/D region 34. Contacts40 through first interlevel dielectric layer 42 make electricalconnection to the first conductive layer 44. A plurality of via layers46 a-46 e through dielectric layers 48 a-48 e, respectively, makeelectrical contact to a plurality of conductive layers 44 and 50 a-50 d,respectively. A top conductive layer 52 is then provided. This isfollowed by a passivation layer 54 composed of USG oxide, for example,deposited by chemical vapor deposition (CVD), for example, to athickness of between about 8000 Å and 20,000 Å. This completes the sealring 62 composed of the conductive layers 44, 50 a-50 d and 52 and vialayers 46 a-46 c. The seal ring 62 makes electrical contact to the deepN-well 32 via contact 40, silicide 38 and S/D region 24. Typical widthsof the seal ring 62 are between about 5 μm to 15 μm.

[0018] A nitride layer 56 composed of Si₃N4 is then conformallydeposited by CVD to a thickness of between about 2000 Å and 10,000 Å.The CVD process provides excellent step coverage along the sidewalls ofthe structure. A polyimide layer 58 is then deposited by spin-ontechniques to a thickness of between about 2 μm and 6 μm.

[0019] When the completed IC is electrically connected in a circuit, thedeep N-well 32 is electrically connected to a positive supply voltage(Vdd) thereby holding the deep N-well 32 and seal ring 62 at signalground. This minimizes signal coupling within the substrate and the S/Dregion.

[0020] Referring now to FIG. 4 showing a top view of a portion of anintegrated circuit 60, a portion of seal ring 62 and an important pointof the present invention is depicted. Notice that there arediscontinuities in the seal ring 62. More specifically, the seal ring 62is spaced further from signal pad 64 and radio frequency circuit 66 thanfrom signal ground pad 68. Typical distances between the seal ring andsignal ground pads would be between about 10 μm and 30 μm, whiledistances between the seal ring and signal pins would be between about20 μm and 50 μm. It should be noted that both DC ground pins and fixedDC voltage supply pins are effectively signal grounds. The additionalspacing between the seal ring 62 and signal pads 64 and radio frequencycircuits 66 reduces the coupling between distinct circuits. The breaksin the seal ring 62 prevent interference from being propagated to othersub-circuits within the integrated circuit. It should also be noted thatpreferably, the seal ring 62 breaks do not overlap along the perimeterof the integrated circuit 60; this further reduces the potential forsignal interference. If the seal ring 60 breaks must overlap (notpreferred), then the distance between the different portions of the sealring must be increased.

[0021] The present invention is achieved by using a method where a sealring is formed by stacking interconnected conductive layers along theperimeter of the IC. Discontinuities formed in the seal ringencapsulating different sections of the IC isolate signals utilized ondifferent sub-circuits within the IC. To further reduce unwanted signalcoupling, the distances between the seal ring and both signal pads andcircuits are enlarged. Electrical connection made between the deepN-well and the seal ring encapsulates the substrate and minimizes signalcoupling to the substrate.

[0022] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of fabricating an integrated circuitseal ring comprising: providing an active area including semiconductordevice structures; and forming a plurality of stacked, interconnected,conductive layers each of which is formed by steps comprising:depositing an inter-metal dielectric layer; etching openings throughsaid inter-metal dielectric layer; filling said openings with aconductive via layer; and depositing and patterning a conductive metallayer to make contact to said conductive via layer filling said openingsin said inter-metal dielectric layer, wherein a first of said conductivevia layers makes electrical contact to signal ground points within thesubstrate of said active area, and wherein each of subsequent saidconductive via layers makes electrical contact to previous patternedsaid conductive metal layer, completing fabrication of said integratedcircuit seal ring.
 2. The method according to claim 1 wherein said sealring is positioned such that signal pads are kept a minimum of 20microns apart from said seal ring.
 3. The method according to claim 2wherein said seal ring is constructed such that discontinuities in saidseal ring occur near said signal pads thereby electrically isolatingdifferent sections of said seal ring.
 4. The method according to claim 1wherein said seal ring is positioned such that radio frequency circuitrycontained within said active area arc kept a minimum of 20 microns apartfrom said seal ring.
 5. The method according to claim 4 wherein saidseal ring is constructed such that discontinuities in said seal ringoccur near radio frequency circuitry contained within said active areathereby electrically isolating different sections of said seal ring. 6.A method of fabricating an integrated circuit seal ring comprising:providing an active area including semiconductor device structureswherein said semiconductor device structures include N-wells and furthercomprise: providing p+ regions within one or more of said N-wells;isolating said p+ regions from said other semiconductor devicestructures by providing a shallow trench isolation region; and forming asalicide region on the surface of said p+ regions thereby providing alow resistance contact to said p+ regions; forming a plurality ofstacked, interconnected, conductive layers each of which is formed bysteps comprising: depositing an inter-metal dielectric layer; etchingopenings through said inter-metal dielectric layer; filling saidopenings with a conductive via layer; and depositing and patterning aconductive metal layer to make contact to said conductive via layerFilling said openings in said inter-metal dielectric layer, wherein afirst of said conductive via layers makes electrical contact to saidsilicide region within the substrate of said active area, and whereineach of subsequent said conductive via layers makes electrical contactto previous patterned said conductive metal layer, completingfabrication of said integrated circuit seal ring.
 7. The methodaccording to claim 6 wherein said seal ring is positioned such thatsignal pads are kept a minimum of 20 microns apart from said seal ring.8. The method according to claim 7 wherein said seal ring is constructedsuch that discontinuities in said seal ring occur near said signal padsthereby electrically isolating different sections of said seal ring. 9.The method according to claim 6 wherein said seal ring is positionedsuch that radio frequency circuitry contained within said active areaare kept a minimum of 20 microns apart from said seal ring.
 10. Themethod according to claim 9 wherein said seal ring is constructed suchthat discontinuities in said seal ring occur near radio frequencycircuitry contained within said active area thereby electricallyisolating different sections of said seal ring.
 11. A method offabricating an integrated circuit seal ring comprising: providing anactive area including semiconductor device structures wherein saidsemiconductor device structures include N-wells and further comprise:providing p+ regions within one or more of said N-wells; isolating saidp+ regions from said other semiconductor device structures by providinga shallow trench isolation region; and forming a salicide region on thesurface of said p+ regions thereby providing a low resistance contact tosaid p+ regions; forming a plurality of stacked, interconnected,conductive layers each of which is formed by steps comprising:depositing an inter-metal dielectric layer; etching openings throughsaid inter-metal dielectric layer; filling said openings with aconductive via layer; and depositing and patterning a conductive metallayer to make contact to said conductive via layer filling said openingsin said inter-metal dielectric layer, wherein a First of said conductivevia layers makes electrical contact to said silicide region within thesubstrate of said active area, and wherein each of subsequent saidconductive via layers makes electrical contact to previous patternedsaid conductive metal layer; depositing a passivation layer overlyingsaid plurality of stacked, interconnected conductive layers; anddepositing a polyimide layer to complete fabrication of said integratedcircuit seal ring.
 12. The method according to claim 11 wherein saidpassivation layer is composed of USG deposited by chemical vapordeposition (CVD) at a thickness of between about 8000 and 20,000Angstroms.
 13. The method according to claim 11 wherein said seal ringis positioned such that signal pads are kept a minimum of 20 micronsapart from said seal ring.
 14. The method according to claim 13 whereinsaid seal ring is constructed such that discontinuities in said sealring occur near said signal pads thereby electrically isolatingdifferent sections of said seal ring.
 15. The method according to claim11 wherein said seal ring is positioned such that radio frequencycircuitry contained within said active area are kept a minimum of 20microns apart from said seal ring.
 16. The method according to claim 15wherein said seal ring is constructed such that discontinuities in saidseal ring occur near radio frequency circuitry contained within saidactive area thereby electrically isolating different sections of saidseal ring.
 17. A method of fabricating an integrated circuit seal ringwherein there are discontinuities in said seal ring forming a pluralityof sections of said seal ring, such that the spacing between signal padsand said seal ring and between radio frequency circuits and said sealring is greater than the spacing between signal ground pads and saidseal ring.
 18. The method according to claim 17 wherein said spacingbetween said seal ring and said signal ground pads is between about 10and 30 microns.
 19. The method according to claim 17 wherein saidspacing between said seal ring and said signal pads is between about 20and 50 microns.
 20. The method according to claim 17 wherein saidspacing between said seal ring and said radio frequency circuits isbetween about 20 and 50 microns.
 21. The method according to claim 17wherein said discontinuities between said plurality of sections of saidseal ring are between about 10 and 30 microns.
 22. The method accordingto claim 17 wherein said seal ring layer is composed of a plurality ofstacked, interconnected, conductive layers each of which is formed bysteps comprising: depositing an inter-metal dielectric layer; etchingopenings through said inter-metal dielectric layer; filling saidopenings with a conductive via layer; and depositing and patterning aconductive metal layer to make contact to said conductive via layerfilling said openings in said inter-metal dielectric layer, wherein afirst of said conductive via layers makes electrical contact to signalground regions within active areas of a semiconductor substrate, andwherein each of subsequent said conductive via layers makes electricalcontact to previous patterned said conductive metal layer.
 23. A methodof fabricating an integrated circuit seal ring comprising: a pluralityof stacked, interconnected, conductive layers each of which is formed bysteps comprising: depositing an inter-metal dielectric layer; etchingopenings through said inter-metal dielectric layer; filling saidopenings with a conductive via layer; and depositing and patterning aconductive metal layer to make contact to said conductive via layerfilling said openings in said inter-metal dielectric layer, wherein afirst of said conductive via layers makes electrical contact to signalground regions within active areas of a semiconductor substrate, andwherein each of subsequent said conductive via layers makes electricalcontact to previous patterned said conductive metal layer and whereinthere are discontinuities in said seal ring forming a plurality ofsections of said seal ring, such that the spacing between signal padsand said seal ring and between radio frequency circuits and said sealring is greater than the spacing between signal ground pads and the sealring.
 24. The method according to claim 23 wherein said spacing betweensaid seal ring and said signal ground pads is between about 10 and 30microns
 25. The method according to claim 23 wherein said spacingbetween said seal ring and said signal pads is between about 20 and 50microns.
 26. The method according to claim 23 wherein said spacingbetween said seal ring and said radio frequency circuits is betweenabout 20 and 50 microns.
 27. The method according to claim 23 whereinsaid discontinuities between said plurality of sections of said sealring are between about 10 and 30 microns.
 28. A seal ring for anintegrated circuit wherein said seal ring is discontinued at theperimeter of said integrated circuit.
 29. The seal ring according toclaim 28 wherein said seal ring is discontinued such that said seal ringforms a plurality of sections of said seal ring and a spacing is formedbetween said plurality of sections of said seal ring.
 30. The seal ringaccording to claim 28 wherein said integrated circuit further comprisessignal pads, ground pads and radio frequency circuits.
 31. The seal ringaccording to claim 30 wherein the spacing between said seal ring andsaid signal pads or said radio frequency circuits is greater than thespacing between said seal ring and said ground pads.
 32. The seal ringaccording to claim 31 wherein the spacing between said seal ring andsaid signal pads or said radio frequency circuits is between about 20and 50 microns.
 33. The seal ring according to claim 31 wherein thespacing between said seal ring and said ground pads is between about 10and 30 microns.
 34. The seal ring according to claim 29 wherein saidspacing between said plurality of sections of said seal ring is betweenabout 10 and 30 microns.